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Verilog HDL数字设计与综合（第二版本科教学版）

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Verilog HDL数字设计与综合（第二版本科教学版）

Name: Verilog HDL数字设计与综合（第二版 本科教学版）
Brand: Jingdong book
SKU: 3101003311
Price: 32.08 USD
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Content Description

本书从用户的角度全面阐述了Verilog HDL语言的重要细节和基本设计方法，并详细介绍了Verilog 2001版的主要改进部分。本书重点关注如何应用Verilog语言进行数字电路和系统的设计和验证，而不仅仅讲解语法。全书从基本概念讲起，并逐渐过渡到编程语言接口以及逻辑综合等高级主题。书中的内容全部符合Verilog HDL IEEE 1364-2001标准。

Author Description

Samir Palnitkar目前是美国Jambo Systems公司总裁。Jambo Systems公司是一流的专用集成电路（ASIC）设计和验证服务公司，专门从事高级微处理器、网络和通信芯片的设计服务。Palnitkar先生曾创办一系列小型的高科技公司。

Catalogue

第一部分 Verilog基础知识
第1章 Verilog HDL数字设计综述 2
1．1 数字电路CAD技术的发展历史 2
1．2 硬件描述语言的出现 2
1．3 典型设计流程 3
1．4 硬件描述语言的意义 4
1．5 VERILOG HDL的优点 5
1．6 硬件描述语言的发展趋势 5
第2章层次建模的概念 7
2．1 设计方法学 7
2．2 四位脉动进位计数器 8
2．3 模块 9
2．4 模块实例 10
2．5 逻辑仿真的构成 12
2．6 举例 12
2．7 小结 15
2．8 习题 16
第3章基本概念 17
3．1 词法约定 17
3．2 数据类型 20
3．3 系统任务和编译指令 25
3．4 小结 29
3．5 习题 30
第4章模块和端口 31
4．1 模块 31
4．2 端口 33
4．3 层次命名 38
4．4 小结 39
4．5 习题 39
第5章门级建模 40
5．1 门的类型 40
5．2 门延迟 50
5．3 小结 54
5．4 习题 55
第6章数据流建模 56
6．1 连续赋值语句 56
6．2 延迟 58
6．3 表达式、操作符和操作数 59
6．4 操作符类型 60
6．5 举例 67
6．6 小结 74
6．7 习题 74
第7章行为级建模 76
7．1 结构化过程语句 76
7．2 过程赋值语句 79
7．3 时序控制 83
7．4 条件语句 88
7．5 多路分支语句 89
7．6 循环语句 91
7．7 顺序块和并行块 94
7．8 生成块 98
7．9 举例 103
7．10小结 108
7．11 习题 109
第8章任务和函数 112
8．1 任务和函数的区别 112
8．2 任务 113
8．3 函数 117
8．4 小结 121
8．5 习题 122
第9章实用建模技术 123
9．1 过程连续赋值 123
9．2 改写（覆盖）参数 125
9．3 条件编译和执行 127
9．4 时间尺度 130
9．5 常用的系统任务 131
9．6 小结 137
9．7 习题 138
第二部分 Verilog高级主题
第10章时序和延迟 142
10．1 延迟模型的类型 142
10．2 路径延迟建模 145
10．3 时序检查 151
10．4 延迟反标注 153
10．5 小结 154
10．6 习题 154
第11章开关级建模 156
11．1 开关级建模元件 156
11．2 举例 160
11．3 小结 164
11．4 习题 165
第12章用户自定义原语 166
12．1 UDP的基础知识 166
12．2 表示组合逻辑的UDP 168
12．3 表示时序逻辑的UDP 173
12．4 UDP表中的缩写符号 176
12．5 UDP设计指南 177
12．6 小结 178
12．7 习题 178
第13章编程语言接口 180
13．1 PLI的使用 182
13．2 PLI任务的连接和调用 182
13．3 内部数据表示 184
13．4 PLI库子程序 185
13．5 小结 195
13．6 习题 196
第14章使用Verilog HDL进行逻辑综合 197
14．1 什么是逻辑综合 197
14．2 逻辑综合对数字设计行业的影响 199
14．3 VERILOG HDL综合 200
14．4 逻辑综合流程 204
14．5 门级网表的验证 210
14．6 逻辑综合建模技巧 212
14．7 时序电路综合举例 217
14．8 小结 224
14．9 习题 224
第15章高级验证技术 226
15．1 传统的验证流程 226
15．2 断言检查 234
15．3 形式化验证 235
15．4 小结 237
第三部分附录
附录A 强度建模和高级线网类型定义 240
附录B PLI子程序清单 243
附录C 关键字、系统任务和编译指令 259
附录D 形式化语法定义 261
附录E Verilog有关问题解答 290
附录F Verilog举例 293
参考文献 303
译者后记 304

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Verilog HDL数字设计与综合（第二版 本科教学版）

Verilog HDL数字设计与综合（第二版本科教学版）