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手把手教你设计CPU——RISC-V处理器篇

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手把手教你设计CPU——RISC-V处理器篇

Name: 手把手教你设计CPU——RISC-V处理器篇
Brand: Jingdong book
SKU: 3118225671
Price: 41.75 USD
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系统介绍RISC-V指令集架构。

结合实际RISC-V开源实例进行教学。

深入剖析RISC-V处理器的微架构以及代码实现。

使读者能够快速掌握并轻松使用RISC-V架构处理器。

通过学习实例蜂鸟E200的Verilog代码，您将能成为一名合格的数字IC设计工程师。通过学习本书推荐的完整开源SoC平台，您也可以快速搭建FPGA原型平台，运行完整的软件实例。

Content Description

本书是一本介绍通用CPU设计的入门书，以通俗的语言系统介绍了CPU和RISC-V架构，力求为读者揭开CPU设计的神秘面纱，打开计算机体系结构的大门。

本书共分为四部分。第一部分是CPU与RISC-V的综述，帮助初学者对CPU和RISC-V快速地建立起认识。第二部分讲解如何使用Verilog设计CPU，使读者掌握处理器核的设计精髓。第三部分主要介绍蜂鸟E203配套的SoC和软件平台，使读者实现蜂鸟E203 RISC-V处理器在FPGA原型平台上的运行。第四部分是附录，介绍了RISC-V指令集架构，辅以作者加入的背景知识解读和注解，以便于读者理解。

本书不仅适合CPU或芯片设计相关从业者阅读使用，也适合作为大中专院校相关师生学习RISC-V处理器设计（使用Verilog语言）和CPU设计的指导用书。

Author Description

胡振波，上海交通大学电子工程系本科、微电子学院硕士。拥有业界多年ASIC和CPU设计与验证经验，先后在Marvell任职ARM架构CPU设计高级工程师、在Synopsys任职研发经理、在比特大陆任职IC设计总监、在武汉聚芯微电子任职架构师，现致力于推动RISC-V架构在国内的传播和发展。

Catalogue

第一部分 CPU与RISC-V综述
第 1章一文读懂CPU之三生三世 2
1.1眼看他起高楼，眼看他宴宾客，眼看他楼塌了——CPU众生相 3
1.3人生已是如此艰难，你又何必拆穿——CPU从业者的无奈 17
1.4无敌是多么寂寞——ARM统治着的世界 18
1.4.1 独乐乐与众乐乐——ARM公司的盈利模式 18
1.4.2 小个子有大力量——无处不在的Cortex-M系列 21
1.4.3 移动王者——Cortex-A系列在手持设备领域的巨大成功 23
1.4.4 进击的巨人——ARM进军PC与服务器领域的雄心 25
1.5东边日出西边雨，道是无晴却有晴——RISC-V登场 25
1.6原来你是这样的“薯片”——ARM的免费计划 28
1.7旧时王谢堂前燕，飞入寻常百姓家——你也可以设计自己的处理器 28

第 2章大道至简——RISC-V架构之魂 29
2.1简单就是美——RISC-V架构的设计哲学 30
2.2RISC-V指令集架构简介 33
2.3RISC-V软件工具链 42
2.4RISC-V和其他开放架构有何不同 44

第3章乱花渐欲迷人眼——盘点RISC-V商业版本与开源版本 46
3.1各商业版本与开源版本综述 47
3.2总结 53
第4章开源RISC-V——蜂鸟E200系列超低功耗Core与SoC 54
4.1与众不同的蜂鸟E200处理器 55
4.2蜂鸟E200简介——蜂鸟虽小，五脏俱全 56
4.3蜂鸟E200型号系列 57
4.4蜂鸟E200性能指标 58
4.5蜂鸟E200配套SoC 59
4.6蜂鸟E200配置选项 60
第二部分手把手教你使用Verilog设计CPU
第5章先见森林，后观树木——蜂鸟E200设计总览和顶层介绍 65
5.1处理器硬件设计概述 66
5.2蜂鸟E200处理器核设计哲学 67
5.3蜂鸟E200处理器核RTL代码风格介绍 68
5.4蜂鸟E200模块层次划分 72
5.5蜂鸟E200处理器核源代码 73
5.6蜂鸟E200处理器核配置选项 73
5.7蜂鸟E200处理器核支持的RISC-V指令子集 74
5.8蜂鸟E200处理器流水线结构 74
5.9蜂鸟E200处理器核顶层接口介绍 74
5.10总结 77

第6章流水线不是流水账——蜂鸟E200流水线介绍 78
6.1处理器流水线概述 79
6.2处理器流水线中的乱序 83
6.3处理器流水线中的反压 84
6.4处理器流水线中的冲突 84
6.5蜂鸟E200处理器的流水线 86
6.6总结 87

第7章万事开头难吗—— 一切从取指令开始 88
7.1取指概述 89
7.2RISC-V架构特点对于取指的简化 97
7.3蜂鸟E200处理器的取指实现 101
7.4总结 116

第8章一鼓作气，执行力是关键——执行 117
8.1执行概述 118
8.2RISC-V架构特点对于执行的简化 121
8.3蜂鸟E200处理器的执行实现 123

第9章善始者实繁，克终者盖寡——交付 161
9.1处理器交付、取消、冲刷 162
9.2RISC-V架构特点对于交付的简化 164
9.3蜂鸟E200处理器交付硬件实现 164

第 10章让子弹飞一会儿——写回 170
10.1处理器的写回 171
10.2蜂鸟E200处理器的写回硬件实现 171

第 11章哈弗还是比亚迪——存储器架构 178
11.1存储器架构概述 179
11.2RISC-V架构特点对于存储器访问指令的简化 183
11.3RISC-V架构的存储器相关指令 184
11.4蜂鸟E200处理器存储器子系统硬件实现 185

第 12章黑盒子的窗口——总线接口单元BIU 203

12.1片上总线协议概述 204
12.2自定义总线协议ICB 206
12.3ICB总线的硬件实现 210
12.4蜂鸟E200处理器核BIU 212
12.5蜂鸟E200处理器SoC总线 214
12.6总结 216

第 13章不得不说的故事——中断和异常 217

13.1中断和异常概述 218
13.2RISC-V架构异常处理机制 221
13.3RISC-V架构中断定义 226
13.4RISC-V架构异常相关CSR寄存器 232
13.5蜂鸟E200异常处理的硬件实现 232

第 14章最不起眼的，其实是最难的——调试机制 246

14.1调试机制概述 247
14.2RISC-V架构的调试机制 249
14.3蜂鸟E200调试机制的硬件实现 251

第 15章动如脱兔，静若处子——低功耗的诀窍 260

15.1处理器低功耗技术概述 261
15.2RISC-V架构的低功耗机制 265
15.3蜂鸟E200低功耗机制的硬件实现 265
15.4总结 275

第 16章工欲善其事，必先利其器——RISC-V可扩展协处理器 276

16.1专用领域架构DSA 277
16.2RISC-V架构的可扩展性 278
16.3蜂鸟E200的协处理器接口EAI 279
16.4蜂鸟E200的协处理器参考示例 286

第三部分使用Verilog进行仿真和在FPGA SoC原型上运行软件

第 17章冒个烟先——运行Verilog仿真测试 292

17.1E200开源项目的代码层次结构 293
17.2E200开源项目的测试用例 294
17.3E200开源项目的测试平台（TestBench） 298
17.4在Verilog TestBench中运行测试用例 299

第 18章套上壳子上路——实现SoC和FPGA原型 302

18.1Freedom E310 SoC简介 303
18.2HBird-E200-SoC简介 304
18.3HBird-E200-SoC FPGA原型平台 311
18.4蜂鸟E200专用FPGA开发板 320

第 19章画龙点睛——运行和调试软件示例 321

19.1Freedom-E-SDK平台简介 322
19.2SIRV-E-SDK平台简介 323
19.3使用SIRV-E-SDK运行示例程序 325
19.4使用GDB和OpenOCD调试示例程序 328
19.5Windows图形化IDE开发工具 331

第 20章是骡子是马？拉出来遛遛——运行跑分程序 332

20.1跑分程序简介 333
20.2Dhrystone简介 333
20.3运行Dhrystone Benchmark 335
20.4CoreMark简介 337
20.5运行CoreMark Benchmark 338
20.6总结与比较 340

附录部分 RISC-V架构详述附录A RISC-V架构指令集介绍 342

附录B RISC-V架构CSR寄存器介绍 374

附录C RISC-V架构的PLIC介绍 384

附录D 存储器模型背景介绍 392

附录E 存储器原子操作指令背景介绍 397

附录F RISC-V指令编码列表 400

附录G RISC-V伪指令列表 404

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