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Jingdong book

计算机科学丛书：逻辑与计算机设计基础（原书第4版）

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Jingdong book

计算机科学丛书：逻辑与计算机设计基础（原书第4版）

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《计算机科学丛书：逻辑与计算机设计基础（原书第4版）》以一台通用计算机为线索，由浅入深地讲解了逻辑设计、数字系统设计和计算机设计。其中，第1章到第5章为逻辑设计，包括数字系统与信息、组合逻辑电路及其设计、算术功能块与硬件描述语言以及时序电路；第6章到第8章为数字系统设计，包括可选的设计话题：数据通路、算术逻辑单元、移位寄存器、一个简单计算机的结构、单周期硬连线控制、多周期硬连线控制等，寄存器与寄存器传输以及存储器基础；第9章到第13章为计算机设计，包括计算机设计基础、指令集结构、RISC与CISC中央处理单元、输入输出与通信以及存储系统。书中附有60个大部分来自现代日常生活中产品设计的真实例子和问题，可以激发读者的学习兴趣。
《计算机科学丛书：逻辑与计算机设计基础（原书第4版）》不仅可以作为计算机科学、计算机工程、电子技术、机电一体化等专业学生学习硬件的一本绝佳教材，也可以作为弱电类工程师和计算机科学工作者的理想参考书籍。
Catalogue

出版者的话
译者序
前言
第1章 数字系统与信息
1.1 信息表示
1.1.1 数字计算机
1.1.2 其他计算机
1.1.3 通用计算机的进一步说明
1.2 数制
1.2.1 二进制
1.2.2 八进制与十六进制
1.2.3 数字范围
1.3 算术运算
1.4 十进制编码
1.5 字符编码
1.5.1 ASCII字符编码
1.5.2 校验位
1.6 格雷码
1.7 本章小结
参考文献
习题

第2章 组合逻辑电路
2.1 二值逻辑和逻辑门
2.1.1 二值逻辑
2.1.2 逻辑门
2.2 布尔代数
2.2.1 布尔代数的基本性质
2.2.2 代数处理
2.2.3 反函数
2.3 标准形式
2.3.1 最小项和最大项
2.3.2 积之和
2.3.3 和之积
2.4 两级电路的优化
2.4.1 成本标准
2.4.2 卡诺图结构
2.4.3 二变量的卡诺图
2.4.4 三变量的卡诺图
2.5 卡诺图的用法
2.5.1 质主蕴涵项
2.5.2 非质主蕴涵项
2.5.3 和之积优化
2.5.4 无关最小项
2.6 程序化的两级优化
2.7 多级电路优化
2.8 其他门类型
2.9 异或操作和异或门
2.10 高阻态输出
2.11 本章小结
参考文献
习题

第3章 组合逻辑电路的设计
3.1 设计过程
3.2 开始分层设计
3.3 工艺映射
3.4 验证
3.4.1 人工逻辑分析
3.4.2 模拟
3.5 组合函数模块
3.6 基本逻辑函数
3.6.1 定值、传输和取反
3.6.2 多位函数
3.6.3 使能
3.7 译码
3.7.1 译码器和使能结合
3.7.2 基于译码器的组合电路
3.8 编码器
3.8.1 优先编码器
3.8.2 编码器的扩展
3.9 选择
3.9.1 多路复用器
3.9.2 基于多路复用器的组合电路
3.10 本章小结
参考文献
习题

第4章 算术功能块与硬件描述语言
4.1 迭代组合电路
4.2 二进制加法器
4.2.1 半加器
4.2.2 全加器
4.2.3 二进制行波进位加法器
4.3 二进制减法
4.3.1 补码
4.3.2 采用二进制补码的减法
4.4 二进制加减法器
4.4.1 有符号的二进制数
4.4.2 有符号二进制数的加法与减法
4.4.3 溢出
4.5 其他的算术功能块
4.5.1 压缩
4.5.2 递增
4.5.3 递减
4.5.4 常数乘法
4.5.5 常数除法
4.5.6 零填充与符号扩展
4.6 硬件描述语言
4.6.1 硬件描述语言
4.6.2 逻辑综合
4.7 硬件描述语言--VHDL
4.8 硬件描述语言--Verilog
4.9 本章小结
参考文献
习题

第5章 时序电路
5.1 时序电路的定义
5.2 锁存器
5.2.1 SR和S R锁存器
5.2.2 D锁存器
5.3 触发器
5.3.1 主从式触发器
5.3.2 边沿触发式触发器
5.3.3 标准图形符号
5.3.4 直接输入
5.4 时序电路分析
5.4.1 输入方程
5.4.2 状态表
5.4.3 状态图
5.4.4 时序电路模拟
5.5 时序电路设计
5.5.1 设计步骤
5.5.2 构建状态图和状态表
5.5.3 状态赋值
5.5.4 使用D触发器的设计
5.5.5 无效状态的设计
5.5.6 验证
5.6 其他类型的触发器
5.7 状态机图及其应用
5.7.1 状态机图模型
5.7.2 输入条件的约束
5.7.3 使用状态机图的设计应用
5.8 时序电路的HDL表示--VHDL
5.9 时序电路的HDL表示--Verilog
5.10 本章小结
参考文献
习题

第6章 选择的设计主题
6.1 设计空间
6.1.1 集成电路
6.1.2 CMOS电路工艺
6.1.3 工艺参数
6.2 门的传播延迟
6.3 触发器定时
6.4 时序电路定时
6.5 异步交互
6.6 同步和亚稳态
6.7 同步电路陷阱
6.8 可编程实现技术
6.8.1 只读存储器
6.8.2 可编程逻辑阵列
6.8.3 可编程阵列逻辑器件
6.9 本章小结
参考文献
习题

第7章 寄存器与寄存器传输
7.1 寄存器与加载使能
7.2 寄存器传输
7.3 寄存器传输操作
7.4 对VHDL和Verilog使用者的提醒
7.5 微操作
7.5.1 算术微操作
7.5.2 逻辑微操作
7.5.3 移位微操作
7.6 对单个寄存器的微操作
7.6.1 基于多路复用器的传输
7.6.2 移位寄存器
7.6.3 行波计数器
7.6.4 同步二进制计数器
7.6.5 其他类型计数器
7.7 寄存器单元设计
7.8 基于多路复用器和总线的多寄存器传输
7.9 串行传输及其微操作
7.10 寄存器传输控制
7.11 移位寄存器和计数器的HDL描述--VHDL
7.12 移位寄存器和计数器的HDL描述--Verilog
7.13 微程序控制
7.14 本章小结
参考文献
习题

第8章 存储器基础
8.1 存储器定义
8.2 随机访问存储器
8.2.1 读写操作
8.2.2 定时波形
8.2.3 存储器特征
8.3 SRAM集成电路
8.4 SRAM芯片阵列
8.5 DRAM芯片
8.5.1 DRAM单元
8.5.2 DRAM位片
8.6 DRAM分类
8.6.1 同步DRAM（SDRAM）
8.6.2 双倍数据速率SDRAM（DDR SDRAM）
8.6.3 Rambus DRAM（RDRAM）
8.7 动态RAM芯片阵列
8.8 本章小结
参考文献
习题

第9章 计算机设计基础
9.1 简介
9.2 数据通路
9.3 算术逻辑运算单元
9.3.1 算术运算电路
9.3.2 逻辑运算电路
9.3.3 算术逻辑运算单元
9.4 移位寄存器
9.5 数据通路描述
9.6 控制字
9.7 一个简单的计算机结构
9.7.1 指令集结构
9.7.2 存储资源
9.7.3 指令格式
9.7.4 指令说明
9.8 单周期硬连线控制
9.8.1 指令译码器
9.8.2 指令和程序举例
9.8.3 单周期计算机观点
9.9 多周期硬连线控制
9.10 本章小结
参考文献
习题

第10章 指令集结构
10.1 计算机体系结构概念
10.1.1 基本计算机操作周期
10.1.2 寄存器组
10.2 操作数寻址
10.2.1 三地址指令
10.2.2 两地址指令
10.2.3 一地址指令
10.2.4 零地址指令
10.2.5 寻址结构
10.3 寻址模式
10.3.1 隐含模式
10.3.2 立即模式
10.3.3 寄存器和寄存器间接模式
10.3.4 直接寻址模式
10.3.5 间接寻址模式
10.3.6 相对寻址模式
10.3.7 变址寻址模式
10.3.8 寻址模式小结
10.4 指令集结构
10.5 数据传送指令
10.5.1 栈指令
10.5.2 独立I/O与存储器映射I/O
10.6 数据处理指令
10.6.1 算术指令
10.6.2 逻辑与位处理指令
10.6.3 移位指令
10.7 浮点数计算
10.7.1 算术运算
10.7.2 移码
10.7.3 标准操作数格式
10.8 程序控制指令
10.8.1 条件分支指令
10.8.2 过程调用与返回指令
10.9 程序中断
10.9.1 中断类型
10.9.2 处理外部中断
10.10 本章小结
参考文献
习题

第11章 RISC和CISC中央处理单元
11.1 流水线数据通路
11.2 流水线控制
11.3 精简指令集计算机
11.3.1 指令集结构
11.3.2 寻址模式
11.3.3 数据通路结构
11.3.4 控制结构
11.3.5 数据阻塞
11.3.6 控制阻塞
11.4 复杂指令集计算机
11.4.1 ISA修改
11.4.2 数据通路修改
11.4.3 控制单元修改
11.4.4 微程序控制
11.4.5 复杂指令的微程序
11.5 其他有关设计
11.5.1 高性能CPU概念
11.5.2 最近的体系结构创新
11.6 本章小结
参考文献
习题

第12章 输入输出与通信
12.1 计算机的I/O系统
12.2 外设举例
12.2.1 键盘
12.2.2 硬盘
12.2.3 液晶显示器
12.2.4 I/O传输速率
12.3 I/O接口
12.3.1 I/O总线与接口部件
12.3.2 I/O接口的例子
12.3.3 选通
12.3.4 握手
12.4 串行通信
12.4.1 同步传送
12.4.2 进一步认识键盘
12.4.3 基于包的串行I/O总线
12.5 传输模式
12.5.1 程序控制传输的例子
12.5.2 中断传输
12.6 中断优先级
12.6.1 菊花链优先级
12.6.2 并行优先级电路
12.7 直接内存访问
12.7.1 DMA控制器
12.7.2 DMA传输
12.8 本章小结
参考文献
习题

第13章 存储系统
13.1 分级存储体系
13.2 访问的局部性
13.3 cache存储器
13.3.1 cache映射
13.3.2 行的大小
13.3.3 cache加载
13.3.4 写方法
13.3.5 概念综合
13.3.6 指令cache和数据cache
13.3.7 多级cache
13.4 虚存
13.4.1 页表
13.4.2 转换后援缓冲器
13.4.3 虚存和cache
13.5 本章小结
参考文献
习题
索引

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$1.66 $1.99 83折
Yami
欣葉
2种选择
欣叶 御大福 芋头麻薯 180g
144

周销量 600+

$1.66 $1.99 83折
Yami
欣葉
2种选择
欣叶 御大福 芋头麻薯 180g
144

周销量 600+

$1.66 $1.99 83折

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