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Jingdong book

国外电子与通信教材系列：数字系统设计与VHDL（英文版）

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Jingdong book

国外电子与通信教材系列：数字系统设计与VHDL（英文版）

Name: 国外电子与通信教材系列：数字系统设计与VHDL（英文版）
Brand: Jingdong book
SKU: 3101011091
Price: 43.94 USD
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Content Description

本书对原著进行了结构调整，使之更适合作为本科双语教学教材。第1章首先回顾了逻辑设计基本原理，第2章和第3章分别讲解了VHDL基本知识和高级主题，第4章为简单设计实例，第5章讨论状态机，第6章讨论浮点数运算，第7章讨论硬件测试和可测试性设计，第8章给出了一些高级设计实例。全书将工业标准硬件描述语言VHDL和数字系统设计融为一体，较好地实现了控制逻辑和运算部件的整合设计，并给出了多个设计实例，便于学生在实践中得到提高。
本书适合作为高等院校电子、电气和计算机专业本科生数字系统设计类课程的双语教学教材，也适合作为相关工程技术人员的参考书。

Author Description

作者：（美国）罗斯（CharlesH.Roth.Jr）（美国）LizyKurianJohn改编：梁松海

CharlesH．Roth，Jr．美国斯坦福大学博士，1961年就职于得克萨斯大学奥斯汀分校，目前是电气与计算机工程系教授。他的授课和研究领域涵盖了数字系统理论和设计、微计算机系统和VHDL应用，出版了4本著作。

Catalogue

Chapter 1 Review of Logic Design Fundamentals1
1.1 Combinational Logic1
1.2 Boolean Algebra and Algebraic Simplification3
1.3 Karnaugh Maps7
1.4 Designing with NAND and NOR Gates10
1.5 Hazards in Combinational Circuits12
1.6 Flip-Flops and Latches14
1.7 Mealy Sequential Circuit Design17
1.8 Moore Sequential Circuit Design25
1.9 Equivalent States and Reduction of State Tables28
1.10 Sequential Circuit Timing30
1.11 Tristate Logic and Busses41
1.12 Problems 42
Chapter 2 Introduction to VHDL51
2.1 Computer-Aided Design51
2.2 Hardware Description Languages54
2.3 VHDL Description of Combinational Circuits57
2.4 VHDL Modules61
2.5 Sequential Statements andVHDL Processes67
2.6 Modeling Flip-Flops Using VHDL Processes69
2.7 Processes Using Wait Statements73
2.8 Two Types of VHDL Delays: Transport and Inertial Delays75
2.9 Compilation, Simulation, and Synthesis of VHDL Code77
2.10 VHDL Data Types and Operators82
2.11 Simple Synthesis Examples84
2.12 VHDL Models for Multiplexers87
2.13 VHDL Libraries90
2.14 Modeling Registers and Counters Using VHDL Processes95
2.15 Behavioral and Structural VHDL101
2.16 Variables, Signals, and Constants111
2.17 Arrays114
2.18 Loops in VHDL117
2.19 Assert and Report Statements119
2.20 Problems122
Chapter 3 Additional Topics in VHDL137
3.1 VHDL Functions137
3.2 VHDL Procedures141
3.3 Attributes143
3.4 Creating Overloaded Operators147
3.5 Multi-Valued Logic and Signal Resolution 148
3.6 The IEEE 9-Valued Logic System153
3.7 SRAM Model Using IEEE 1164156
3.8 Model for SRAM Read/Write System158
3.9 Generics161
3.10 Named Association162
3.11 Generate Statements163
3.12 Files and TEXTIO165
3.13 Problems169
Chapter 4 Design Examples1 77
4.1 BCD to Seven-Segment Display Decoder178
4.2 A BCD Adder179
4.3 32-Bit Adders181
4.4 Traffic Light Controller188
4.5 State Graphs for Control Circuits191
4.6 Scoreboard and Controller192
4.7 Synchronization and Debouncing195
4.8 A Add-and-Shift Multiplier197
4.9 Array Multiplier203
4.10 A Signed Integer/Fraction Muliplier206
4.11 Keypad Scanner218
4.12 Binary Dividers226
4.13 Problems236
Chapter 5 SM Charts and Microprogramming247
5.1 State Machine Charts247
5.2 Derivation of SM Charts252
5.3 Realization of SM Charts262
5.4 Implementation of the Dice Game266
5.5 Problems271
Chapter 6 Floating-Point Arithmetic 2 78
6.1 Representation of Floating-Point Numbers278
6.2 Floating-Point Multiplication284
6.3 Floating-Point Addition294
6.4 Other Floating-Point Operations300
6.5 Problems301
Chapter 7 Hardware Testing and Design for Testability306
7.1 Testing Combinational Logic306
7.2 Testing Sequential Logic311
7.3 Scan Testing314
7.4 Boundary Scan317
7.5 Built-In Self-Test328
7.6 Problems339
Chapter 8 Additional Design Examples345
8.1 Design of a Wristwatch345
8.2 Memory Timing Models356
8.3 A Universal Asynchronous Receiver Transmitter364
8.4 Problems378
Appendix A383
VHDL Language Summary
Appendix B391
IEEE Standard Libraries
Appendix C393
TEXTIO Package
Appendix D 395
Projects
References406

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